{
  "board": {
    "cellMm": 0.5,
    "cols": 20,
    "copperUm": 35.0,
    "copperUmByLayer": {
      "B.Cu": 35.0,
      "F.Cu": 35.0,
      "In1.Cu": 35.0,
      "In2.Cu": 35.0
    },
    "description": "",
    "dielectricMm": [
      0.2,
      1.065,
      0.2
    ],
    "heightMm": 10.0,
    "layers": [
      "F.Cu",
      "In1.Cu",
      "In2.Cu",
      "B.Cu"
    ],
    "name": "",
    "rows": 20,
    "thicknessMm": 1.605,
    "widthMm": 10.0,
    "x0": 0.0,
    "y0": 0.0
  },
  "chips": [],
  "fixPlan": [],
  "flow": {
    "cellMm": 0.5,
    "cols": 20,
    "file": "flow.bin",
    "jMax": 0.1931760983119318,
    "layers": [
      "F.Cu",
      "In1.Cu",
      "In2.Cu",
      "B.Cu"
    ],
    "layout": "for each layer in order: jx, jy (A/mm², physical sense, +x right, +y down the board as KiCad), volt (V; NaN off copper or where the rail is unknown), net (index into nets, -1 off copper); each float32 little-endian, rows*cols, row-major from (x0, y0)",
    "method": "The DC solve per loaded net, signed: current enters at the source terminals and leaves at the sinks (a ground returns to its connector; the spec's `sources` names the part a net is fed from). Voltage = the net's rail at its anchor plus the solved IR drop; the rail comes from the spec's `voltages` or the net's name. A switching node is drawn as a tide between its rails at a slowed, stated rate.",
    "nets": [
      {
        "amps": 0.025,
        "dropV": 0.00001857476615896303,
        "ground": false,
        "loaded": true,
        "name": "3V3",
        "note": null,
        "railV": 3.3,
        "sense": "from J1 to U1",
        "switching": null,
        "terminals": [
          {
            "amps": 0.025,
            "pad": "1",
            "ref": "J1",
            "role": "source",
            "x": 2.0,
            "y": 5.0
          },
          {
            "amps": 0.025,
            "pad": "1",
            "ref": "U1",
            "role": "sink",
            "x": 8.0,
            "y": 5.0
          }
        ],
        "vias": [],
        "voltKnown": true,
        "voltRange": [
          3.2999821484336413,
          3.3000007231998003
        ]
      }
    ],
    "rows": 20,
    "topRailV": 3.3,
    "voltMax": 3.3000007231998003,
    "voltMin": 3.2999821484336413,
    "x0": 0.0,
    "y0": 0.0
  },
  "heat": {
    "budgetC": 60.0,
    "jouleW": 0.0,
    "movingAirWPerM2K": 25.0,
    "peakRiseC": 0.0000723906559869647,
    "peakRiseMovingC": 0.00003783713691518642,
    "stillAirWPerM2K": 10.0,
    "tabW": -0.0
  },
  "heatsinks": [],
  "inputIdentity": {
    "algorithm": "sha256",
    "board": "d2171f567cd4c420208e8419bff846a1f0a212270696b946c5edb2a20ca1d23d",
    "solverVersion": "0.7.15",
    "spec": "f5964649107ae44a9493804647bad57a071db403ec165aab5256dfcbba1aa2fd"
  },
  "issues": [],
  "log": [
    "3V3: 0.025 A, 4 layer(s), 70 iterations, residual 8.4e-8",
    "heat, still air: 144 iterations, residual 8.9e-8",
    "heat, moving air: 137 iterations"
  ],
  "method": "Copper fraction per cell from the board's filled polygons, tracks, pads and vias; DC conduction per loaded net between its terminals (σ 5.8e4 S/mm × thickness); heat: four layers coupled through the dielectric and every via barrel, copper 0.40 W/mm·K, FR4 0.3/0.6 W/m·K, 10 (still) or 25 (moving) W/m²K to the air on both faces; one steady-state solve each. Optional rectangular heatsinks use a 3D finite-volume conducting block with specified conductivity, contact resistance and air loss on exposed faces. Copper thickness may differ by layer; Joule heat is deposited on its source layer. This remains a screening model: rectangular board outline, prescribed chip watts and convection; no fins, radiation, airflow solve or junction-temperature qualification.",
  "nets": [
    {
      "amps": 0.025,
      "copperMm2": 30.0,
      "iterations": 70,
      "jouleW": 0.0,
      "layers": [
        "F.Cu",
        "In1.Cu",
        "In2.Cu",
        "B.Cu"
      ],
      "net": "3V3",
      "peakAt": [
        6.75,
        5.25
      ],
      "peakJ": 0.2,
      "peakLayer": "F.Cu",
      "vias": 0
    }
  ],
  "pads": [
    {
      "net": "3V3",
      "pad": "1",
      "ref": "J1",
      "x": 2.0,
      "y": 5.0
    },
    {
      "net": "3V3",
      "pad": "1",
      "ref": "U1",
      "x": 8.0,
      "y": 5.0
    }
  ],
  "partValues": {},
  "pourNets": [
    {
      "copperMm2": 30.0,
      "net": "3V3"
    }
  ],
  "review": {
    "converter": null,
    "decoupling": [],
    "esd": [],
    "noise": {
      "cavities": [],
      "crosstalk": [],
      "tones": []
    },
    "pdn": {
      "note": "no ground net",
      "rails": []
    },
    "rails": [
      {
        "dropMv": 0.02,
        "dropPct": 0.0,
        "net": "3V3",
        "railV": 3.3
      }
    ],
    "reference": []
  },
  "scales": {
    "jHi": 1.0,
    "jMax": 0.19317609071731567,
    "qHi": 0.009999999776482582,
    "qMax": 2.2338298322210903e-8,
    "tHi": 1.0,
    "tMax": 0.0000723906559869647,
    "tMovingMax": 0.00003783713691518642
  },
  "seconds": 0.0,
  "signals": {
    "capacitance": [],
    "differentialPairs": [],
    "method": "Screening estimates, not signal-integrity signoff. Outer-layer equal-width microstrip only; sampled reference coverage and parallel partner gaps. No solder mask, pads, packages, loss, dispersion, crosstalk, S-parameters or eye diagrams.",
    "sampleMm": 0.25,
    "sources": [
      "https://www.ti.com/lit/an/slva531a/slva531a.pdf",
      "https://www.ti.com/seclit/eb/slyw038c/slyw038c.pdf"
    ]
  },
  "source": {
    "board": "/home/adom/project/nrf52832-hx711/docs/tool-defects/fields-layers/fixture.kicad_pcb",
    "spec": "nrf52832-hx711/docs/tool-defects/fields-layers/spec.json"
  },
  "textures": [
    "copper-F_Cu.png",
    "J-F_Cu.png",
    "q-F_Cu.png",
    "T-F_Cu.png",
    "Tm-F_Cu.png",
    "q-3V3-F_Cu.png",
    "J-3V3-F_Cu.png",
    "copper-In1_Cu.png",
    "J-In1_Cu.png",
    "q-In1_Cu.png",
    "T-In1_Cu.png",
    "Tm-In1_Cu.png",
    "q-3V3-In1_Cu.png",
    "J-3V3-In1_Cu.png",
    "copper-In2_Cu.png",
    "J-In2_Cu.png",
    "q-In2_Cu.png",
    "T-In2_Cu.png",
    "Tm-In2_Cu.png",
    "q-3V3-In2_Cu.png",
    "J-3V3-In2_Cu.png",
    "copper-B_Cu.png",
    "J-B_Cu.png",
    "q-B_Cu.png",
    "T-B_Cu.png",
    "Tm-B_Cu.png",
    "q-3V3-B_Cu.png",
    "J-3V3-B_Cu.png"
  ],
  "thermalConvergence": {
    "movingResidual": 8.908406430245977e-8,
    "stillResidual": 8.851885298009464e-8
  },
  "vias": []
}