{
  "batteryLifeRequirement": {
    "status": "29-62day provisional duty-cycle scenarios; rotor cell qualification pending"
  },
  "board": "28x70 bare nRF52832 HX711 TPS63900 external LS14500 prototype",
  "clearance": 0.15,
  "clearanceNote": "0.15mm routing clearance gives0.05mm margin above JLCPCB0.10mm minimum while allowing0.4mm pitch QFN pin escapes; native gate retains fabrication rules.",
  "copperUm": 35,
  "edgeClearance": 0.3,
  "fab": {
    "layers": 2,
    "rules": "jlcpcb",
    "target": "jlcpcb"
  },
  "fixedRefs": [
    "U1",
    "J1",
    "J2",
    "J3",
    "AE1",
    "J4",
    "Y1",
    "L2",
    "C18",
    "R13",
    "R14",
    "J5",
    "H1",
    "H2",
    "H3",
    "H4"
  ],
  "hot": {
    "U1": {
      "maxRiseC": 5,
      "tabNet": "GND",
      "watts": 0.04,
      "at": [
        13.0,
        22.0
      ]
    },
    "U2": {
      "maxRiseC": 5,
      "tabNet": "GND",
      "watts": 0.005,
      "at": [
        11.525,
        41.635
      ]
    },
    "U3": {
      "maxRiseC": 5,
      "tabNet": "GND",
      "watts": 0.015,
      "at": [
        14.0,
        59.0
      ]
    }
  },
  "hotNote": "Conservative instantaneous active-case screening; duty-cycled average heat is lower. This does not validate battery life.",
  "inheritedErrors": 0,
  "loads": {
    "3V3": {
      "amps": 0.025,
      "maxRiseC": 5,
      "terminals": [
        {
          "reference": "U3",
          "pad": "6",
          "amps": 0.025
        },
        {
          "reference": "U4",
          "pad": "1",
          "amps": -0.014
        },
        {
          "reference": "U1",
          "pad": "13",
          "amps": -0.0036666666666666666
        },
        {
          "reference": "U1",
          "pad": "36",
          "amps": -0.0036666666666666666
        },
        {
          "reference": "U1",
          "pad": "48",
          "amps": -0.0036666666666666666
        }
      ]
    },
    "SENSOR_3V3": {
      "amps": 0.014,
      "maxRiseC": 5,
      "terminals": [
        {
          "reference": "U4",
          "pad": "6",
          "amps": 0.014
        },
        {
          "reference": "J1",
          "pad": "1",
          "amps": -0.009428571428571429
        },
        {
          "reference": "U2",
          "pad": "1",
          "amps": -0.0015238095238095239
        },
        {
          "reference": "U2",
          "pad": "3",
          "amps": -0.0015238095238095239
        },
        {
          "reference": "U2",
          "pad": "16",
          "amps": -0.0015238095238095239
        }
      ]
    },
    "VBAT_PROTECTED": {
      "amps": 0.05,
      "maxRiseC": 5,
      "terminals": [
        {
          "reference": "J5",
          "pad": "1",
          "amps": 0.05
        },
        {
          "reference": "U3",
          "pad": "10",
          "amps": -0.049999
        },
        {
          "reference": "U3",
          "pad": "1",
          "amps": -1e-06
        }
      ]
    }
  },
  "minTrackWidth": 0.15,
  "notPoured": [
    "AIN_P",
    "AIN_N",
    "BRIDGE_P",
    "BRIDGE_N",
    "RF_CHIP",
    "RF50",
    "ANT_PCB",
    "ANT_EXT",
    "XC1",
    "XC2",
    "DEC1",
    "DEC3",
    "DEC4",
    "LX1",
    "LX2",
    "CFG1",
    "CFG2",
    "CFG3"
  ],
  "outline": {
    "cornerRadius": 1
  },
  "planeUnder": [
    {
      "layer": "B.Cu",
      "name": "Continuous RF and crystal reference ground",
      "net": "GND",
      "polygon": [
        [
          6,
          11.700000000000003
        ],
        [
          22,
          11.700000000000003
        ],
        [
          22,
          26.5
        ],
        [
          6,
          26.5
        ]
      ]
    }
  ],
  "planes": {},
  "pours": [
    {
      "connection": "solid",
      "layers": [
        "F.Cu",
        "B.Cu"
      ],
      "name": "GND return",
      "net": "GND",
      "outline": true,
      "priority": 0,
      "thermalBridge": 0.3,
      "thermalGap": 0.25
    }
  ],
  "requireEvidence": [
    "calcs",
    "simulation"
  ],
  "solidAt": [
    "U1.31",
    "U1.45",
    "U1.49",
    "U3.11"
  ],
  "stub": 0.15,
  "thermalVias": [
    {
      "pad": "U3.11",
      "net": "GND",
      "count": 1
    }
  ],
  "wideNets": {
    "3V3": [
      0.5,
      0.3,
      0.15
    ],
    "ANT_EXT": [
      0.25
    ],
    "ANT_PCB": [
      0.25
    ],
    "DEC1": [
      0.15
    ],
    "DEC3": [
      0.15
    ],
    "DEC4": [
      0.15
    ],
    "GND": [
      0.5,
      0.3,
      0.15
    ],
    "HX_DOUT": [
      0.15
    ],
    "RESET_N": [
      0.15
    ],
    "RF50": [
      0.25
    ],
    "RF_CHIP": [
      0.15
    ],
    "SCK_MCU": [
      0.15
    ],
    "SENSOR_3V3": [
      0.4,
      0.3,
      0.2
    ],
    "SENSOR_EN": [
      0.15
    ],
    "SWCLK": [
      0.15
    ],
    "SWDIO": [
      0.15
    ],
    "UART_RX": [
      0.15
    ],
    "UART_TX": [
      0.15
    ],
    "XC1": [
      0.15
    ],
    "XC2": [
      0.15
    ],
    "VBAT_PROTECTED": [
      0.6,
      0.4,
      0.25
    ],
    "LX1": [
      0.4,
      0.3,
      0.2
    ],
    "LX2": [
      0.4,
      0.3,
      0.2
    ]
  },
  "sources": {
    "3V3": [
      "U3"
    ],
    "SENSOR_3V3": [
      "U4"
    ],
    "VBAT_PROTECTED": [
      "J5"
    ]
  },
  "voltages": {
    "3V3": 3.3,
    "SENSOR_3V3": 3.3,
    "VBAT_PROTECTED": 3.6
  },
  "routerExclusionNote": "Virtual __NO_COPPER__ reservation in planeUnder is a router workaround for native keepouts ignored by the grid router. It is not a copper plane or a circuit net. Native keepouts remain unchanged and native DRC is required.",
  "poursNote": "Actual accepted native ground pours use solid pad connections. Temporary virtual-net grid-router exclusions removed after routing; native antenna and RF-return keepouts remain in PCB and native DRC. They are not electrical nets or production rule areas.",
  "stackupMm": [
    1.53
  ],
  "dcMaxIterations": 20000,
  "candidateNote": "Experimental physical two-layer solver. 1.53mm dielectric plus two nominal 35um copper faces gives 1.6mm. Load allocations are explicit screening assumptions, not measured pin currents.",
  "allocationLimits": "3V3: 14mA sensor feed plus 11mA split equally among MCU supplies. Sensor: 350ohm excitation at J1 plus remaining budget split across HX711 supply pins. Battery: 1uA assumed EN branch, remainder VIN. Ground-return network, transient currents and package-internal sharing are not solved by these rail cases.",
  "heatPlacementNote": "Concentrated source sensitivity at U1 exposed pad49, U3 exposed pad11 and U2 ground lead5. The solver spreads input over a 1.2mm-radius disk; this is not a package thermal model. Compare separately from default split-across-ground-pads results.",
  "hotMaxRiseC": 5,
  "budgetAdapterNote": "Candidate uses a global thermal budget. Use the strictest original per-device limit; do not increase any acceptance limit.",
  "thermalViaReview": {
    "originalGenericCount": 6,
    "reviewedExposedPadNeighbourhoodCount": 1,
    "nearAnyU3GroundPadCount": 3,
    "basis": "Prior documented AIFlow thermal-via acknowledgement retains existing layout at 15mW; geometric audit reconciles one via near U3.11 versus three near any U3 ground pin. This provision count is not a cooling qualification. All 5C thermal budgets retained.",
    "evidence": "docs/via-count-review.md",
    "status": "Integration candidate; not promoted to production"
  }
}